1. Field of the Invention
The present invention relates generally to frequency synthesis and particularly, but not exclusively, relates to frequency- and phase-locked loops.
2. Description of the Related Art
Frequency-locked loops, or alternatively phase-locked loops (FLLs and PLLs respectively), are blocks that perform the function shown in FIG. 1. That is, an input signal at a fixed first frequency Fin is supplied to the FLL 10, and the FLL outputs a signal at a fixed second frequency Fout that is not equal to Fin. This general principle is known as frequency synthesis.
It is advantageous to realize as much of the FLL as possible in digital, due to the benefits that are inherent with digital processing (i.e. cheaper, smaller die area, rapid testability, etc).
FIG. 2 shows an implementation of an FLL 20. A digital signal having a frequency Fin is input to a frequency detector 22. The frequency detector 22 detects the frequency of the input signal, compares it with the frequency of a fed-back signal, and outputs a further digital signal that is indicative of the difference in the two frequencies. This signal is input to a loop filter 24 which has an integrating function, and outputs a digital integrated signal. In the majority of FLLs, the digital integrated signal preferably has a high resolution such that the FLL works accurately. Signals of the order of 20 bits or more are typical.
The integrated signal is input to a DAC 26, which converts it to an analog signal which controls a voltage-controlled oscillator 28 (VCO). The frequency of the output signal from the VCO 28 is controlled by its input signal. A high input signal leads to a high-frequency output signal, and vice versa. The signal output from the VCO 28 is fed to a ÷N block 29. The frequency Fout of the output signal is divided by a factor N, which is chosen by the designer of the system, and the signal containing this divided frequency is fed back to the frequency detector 22. In this way the system converges to an output signal with a frequency of Fout=N×Fin.
As aforementioned, the output of the loop filter 24 must have a high resolution in order for the DAC to operate correctly, of the order of 20 bits. However, designing a 20-bit DAC is extremely difficult.